Verified
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IdentityWelcome to my profile! I hope you have a strong zeal to know about me. Here my profile:-
Technical skills:-
-skilled in operating HPLC and GCMS and analyzing the purity of the material through chromotograph.
synthesis:-Experience working with synopsis design compiler for synthesis.
Physical design flow:-floor planning,Placement and routing, clock tree synthesis,Static Timing Analysis,Design Rule Check, Layout vs schematic
Tools used :- Cadence, microwind , magic,
virtuoso cadence encounter for floor planning,APR and Clock tree synthesis, synopsis Prime time for timing analysis and power optimization, modelsim
RTL coding and Verification:- Strong verilog RTL programming skill, verification using system verilog, functional verification, constraint random verification, assertion based verification,PLC,SCADA
-Saurabh Tanwar is currently pursuing his master's in electrical engineering from Texas A & M university kingsville. He has a profound knowledge in depth in the field of VLSI design and have gone through VHDL programming.
-He had studied various computer architecture courses like gpu and its cuda core programming where how there is a interaction between cpu( host) and the gpu(device) with the use of blocks as a part of grid through C and has a brief insight in super pipelining, superscalar and parallel processors and also deals with problems related to cache coherence.
-Besides all of these, he basically deals with issues related to networking and have gone through the CCNA courses which include routing protocol such as BGP, RIP, EIGRP and OSPF.
-All apart of these, he has studied microwave engineering, wireless communication and satellite communication and done project on Artificial intelligence based neural robot.
After all, he has a hands on programming based on C, C++,verilog,system verilog ,java, Java script, ruby on rails and Python based programming language and skilled in html and css.
