Tejaswini

Over the past five years, my professional focus has been on VLSI Physical Design and Analog Layout. My expertise encompasses industry-standard Electronic Design Automation (EDA) tools, including ICC2, Innovus, ICC Custom Compiler, Cadence Virtuoso, Primetime, and Tempus. I possess a strong proficiency in scripting languages such as UNIX, TCL, and Perl, which I leverage to automate and optimize intricate design workflows. My project experience includes working with advanced technology nodes (5nm, 4nm, 3nm).

In Analog Layout, I have specialized in Floorplanning, Power, Bump, and Clock route planning, as well as mitigating process mismatches through advanced matching techniques, including common centroid, inter-digitation, and dummy cell insertion. I have contributed to design change projects involving SerDes (PLL) and have demonstrated expertise in resolving Design Rule Check (DRC) and Layout Versus Schematic (LVS) violations.

Currently, in my role as a Physical Design Engineer, I have developed expertise in Place and Route (PNR) block implementation, full-chip Static Timing Analysis (STA) signoff, and System Design Constraints (SDC) development. I have successfully executed Engineering Change Orders (ECOs) and contributed to tape out procedures for critical project blocks.

Driven by a commitment to semiconductor technology advancement, I actively seek opportunities for professional collaboration. I am particularly interested in partnerships that push the boundaries of current semiconductor capabilities. I welcome engagement with individuals and organizations dedicated to innovation in this field.