Mohammed Adil

Currently working as a verification engineer. Expert in SystemVerilog constructs and UVM. Experienced in writing verification environment using SystemVerilog following Universal Verification Methodology (UVM). Having in-depth understanding of AMBA bus protocols like APB, AHB and AXI. My teaching method includes less ppt and more live coding examples. Picking up real time projects and building foundational understanding from it. By the end of the course you will have a understanding of a test plan, how to implement a complete test environment using the language and complete verification flow with a major project. Course will also include design and verification using Verilog and creating a self-checking testbench from pure Verilog and than slowly implementing it in SystemVerilog and than introducing UVM. By the end of the verilog module you will have a confidence to design circuits using just 4 modules (Vectored mux, vectored comparator, vectored adder and vectored D flip-flop). All the relevant materials and recordings will be shared for reference.